1. Field of the Invention
The present invention relates to a logic simulation method for logically verifying a logic circuit designed through sequential processing descriptions processes.
2. Description of the Related Art
Recently, sequential processing descriptions have been used widely for describing the functions of a logic circuit, input patterns to a logical circuit, etc. in addition to conventional descriptions of a net list of the logical circuit. The time taken for verifying a logic circuit increases corresponding to the expansion in the size of the circuit, and there is a demand on reducing this time.
The time taken for logically verifying a logic circuit which is described by a net list has been shortened by accelerating the execution speed of logic simulation using an exclusive high-speed unit-delay event-driven logic simulator. However, since the exclusive machine can only simulate a net list, the descriptions of the net list must be extracted and simulated or all descriptions must be replaced with a net list through a technology of synthesizing a circuit to perform a logic simulation when a logic circuit designed through a functional description is verified.
In a logic simulation of a logical circuit described based on a function level and designed through sequential processing descriptions, an exclusive simulator cannot be used for shortening the time taken for a logical verification.